Many different types of memory cell designs exist in the integrated circuitry art, each with its own advantages and disadvantages. For example, a traditional dynamic random access memory (DRAM) cell comprises a capacitor for storing charge representative of a logic ‘0’ or ‘1’ state, and an access transistor for accessing such charge and sending it via a bit line to a sensing circuit. Such a cell design is beneficial in that it can be made relatively dense, and hence many such cells can be placed on a given integrated circuit, amounting in large amounts of memory.
That being said, traditional DRAM cells are not optimal. As just noted, such cells require two elements per cell—the capacitors and the access transistor. While many different DRAM cell designs exist with the goal of reducing the area such cells take up on the surface of an integrated circuit, the reality is that accommodating two elements per cell comprises a significant sizing issue.
In one approach to making smaller memory cells, it has been proposed to use thyristors as the storage element in a memory cell. A thyristor essentially comprises two diodes in series, or what is sometimes referred to as a PNPN structure, which reflects that the device is formed by doping of alternating polarities (P and N). As has been noted in the prior art, thyristor-based cells can be used to selectively store charge, and hence such cells are useable as memory cells. For example, charge can be stored by causing the junctions within the structure to become reversed biased, and such selective storage can be facilitated by gating the thyristor.
However, even thyristor-based memory cell designs are non optimal. Some require or use, in addition to a thyristor gate, an additional access transistor gate for selectively allowing charge transfer between the bit line and the thyristor. Such cell designs therefore suffer from the same drawback as traditional DRAM cells in that they require two devices—an access transistor, and the gated thyristor. In thyristor-based cells not having an access transistor, previous structures still generally take up inordinate amounts of area on the surface of the integrated circuit, for example, because the thyristor is built planar (i.e., horizontally) in the substrate of the integrated circuit. Moreover, such thyristor-based cells not having access transistors have been touted as replacements for traditional SRAM cells, and it is not believed that such cells have been designed as DRAM cells, which are preferable to SRAM cells in many applications. Still other thyristor designs require the device's substrate to be isolated from the bulk substrate, for example, by using a buried oxide (Box) or by using a SOI (silicon-on-insulator) substrate. Using such specialized substrates adds complexity and cost to the manufacture of the thyristor-based cell.
In short, the memory cell art would be benefited from an improved thyristor cell design similar in functionality to a DRAM cell, and such a cell design would be small, would not require additional devices such as access transistors, and would be easily and cheaply manufactured. Embodiments of such a cell design are disclosed herein.